发明名称 TEST STATE AND INITIAL STATE SETTING CIRCUIT
摘要 PURPOSE:To attain to enhance the function of an IC appratus and the degree of freedom thereof at the time of planning, by setting the levels of the output signals from a plurality of comparators corresponding to the difference of voltage supplied to an external terminal and setting test and initial states respectively. CONSTITUTION:When a power source is turned ON to an IC apparatus, reference voltages VA, VB, VC are generated and charging is performed in dependence on the time constant by a resistor (r) and an externally attached capacitor 10 and the voltage VD of the external terminal 3 also rises from zero to voltage VC. This raised voltage VC is compared with voltages VA, VB by comparators 1, 2 and, when VD<VB, an ''H'' level signal is outputted from a terminal 9 to set the initial state of IC. When an external power source is applied to the terminal 3 to forcibly set VD to VA or more, the output of the comparator 1 comes to an ''H'' level and a delay circuit 6 outputs a test signal to bring IC connected to a terminal 8 to a test mode.
申请公布号 JPS60190877(A) 申请公布日期 1985.09.28
申请号 JP19840045430 申请日期 1984.03.12
申请人 HITACHI SEISAKUSHO KK 发明人 MOGI YASUHIDE;AZUMA NOBUO
分类号 G01R31/28;G01R31/316;H03K19/0175 主分类号 G01R31/28
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