发明名称 REPRODUCING CIRCUIT FOR DIGITAL SIGNAL
摘要 PURPOSE:To reduce the scale of a digital signal reproducing circuit by outputting the word weight of data after 8-8 conversion in the form of an eight-level analog voltage value corresponding to the number of ''1''s in one word of reproduced data. CONSTITUTION:A video signal is supplied to an A/D converter 2 through an input terminal 1, sampled with a clock of about 10 MHz and then converted into an eight-bit digital signal as the 1st data; and this 1st data is converted by a converter 3 according to an 8-8 conversion rule to output the 2nd data. Further, an inverting circuit 4 the 2nd data as it is as odd-numbered data and converts even-numbered words into the 3rd data wherein ''1'' and ''0'' are inverted, and this 3rd data is supplied to a converter 5, which converts the 8-bit parallel data into serial data. A synchronizing data adding circuit 6 adds synchronizing data and the resulting data is recorded on a magnetic tape 8. Reproduced serial data is inputted to a synchronizing data detecting circuit 9 during reproduction to generate an inverted pulse B. Further, the reproduced data A is supplied to a simple demodulating circuit 10 to obtain an analog level output 11. Consequently, the digital data is reproduced as the 8-level analog signal.
申请公布号 JPS60191476(A) 申请公布日期 1985.09.28
申请号 JP19840045470 申请日期 1984.03.12
申请人 HITACHI SEISAKUSHO KK;HITACHI BIDEO ENGINEERING KK 发明人 SHIONO HIROSHI;IZUMIDA MORIJI;MITA SEIICHI;UMEMOTO MASUO;TAKAGI HITOSHI
分类号 G11B20/10;G11B20/14;H04N5/92 主分类号 G11B20/10
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