| 摘要 |
PURPOSE:To reduce the scale of a hardware by reducing the number of delay circuits, in the test of IC, by compensating the delay error between passages by using a variable delay circuit having two-stage constitution. CONSTITUTION:Logical data and a polarity indication signal are applied to an EXOR gate 12 and the output of the gate 12 sets FF351-35m through coincidence selection circuits 14-16, variable delay circuits 42-44, an OR gate 45 and variable delay circuits 461-46m and further resets FF351-35m through coindidence selection circuits 17-19,... and variable delay circuits 521-52m. In this case, delay errors between passages reaching OR gates are removed by adjusting delay circuits 42-44, 47-49 and the outputs thereof are supplied to variable delay circuits 461-46m, 521-52m to respectively adjust errors between passages of the rising and falling of a logical wave form in the output sides of drive circuits 411-41m. |
