| 摘要 |
<p>A data processing system has an arithmetic logic unit that includes a plurality of summation units for summing an ADDEND with a AUGEND to obtain a first signal that represents the summation of the ADDEND, AUGEND and a CARRY IN. Each summation units also provides a second signal that represents the carry of the summation of the ADDEND and the AUGEND. The plurality of summation units are arranged in a second plurality of groups of less than a third preselected number of summation units with over to the carry in such that each member group has a carry a serial connection of the carry in for receipt of a carry out from a preceding group's carry out. Interdisposed between the groups is a fourth plurality of carry boost units for boosting the second signal of a preceding group prior to application to a following group. Each summation unit includes a carry advance node which is driven to a predetermined voltage when the ADDEND and AUGEND do not indicate a carry propagate condition. The carry advance nodes of the summation units within each group are coupled, together. A carry advance circuit detects when the coupled carry advance nodes are not at the predetermined voltage, indicating that all the summation units provide a carry propagate condition. In this event the carry in of the group of summation units is applied to the carry in of the next group of summation units overriding the output of the carry boost circuit. A similar carry backward circuit operates under the same conditions to apply the carry in of the group of summation units to the carry out of that group.</p> |
