发明名称 MEMORY ACCESS CONTROL SYSTEM
摘要 <p>PURPOSE:To omit a ROM and to cope with the change or the like of a system constitution efficiently by storing information for initial program loading in a readable/writable memory. CONSTITUTION:When the rising operation of a sub-processor 11 side is to be executed by a main processor 10 side, the main processor 10 sets up an address conversion circuit 14 and a selection circuit 15 and then sends a start signal to the bus-processor 11 through a register 16 and the sub-processor 11 starts its reading operation from X'0000'. The information of X'0000' on an address bus 23 is converted at its address into address information actually accessing a common memory 12 by the address conversion circuit 14. Since common memory access mode information is set up in the selection circuit 15 and the X'0000' is included in a prescribed address range, a selection line 29 is turned on and the common memory 12 is turned to a selecting state when the memory is accessed from the sub-processor 11. Data are inputted through a bus 22, a try state circuit 19 and a bus 24.</p>
申请公布号 JPS60189561(A) 申请公布日期 1985.09.27
申请号 JP19840045038 申请日期 1984.03.09
申请人 PANA FACOM KK 发明人 HASEBE ISAMU;KITAZAWA SATORU
分类号 G06F15/16;G06F9/445;G06F12/00;G06F12/06;G06F15/177 主分类号 G06F15/16
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