| 摘要 |
PURPOSE:To prevent effectively a system from being complicated and to shorten effectively the data processing time and the bus use time by dividing the execution cycle of one instruction to two or more phases to update data. CONSTITUTION:When receiving an address signal ADR and a data update command RNW from a processor, a memory control circuit 21 switches switch circuits 41 and 43 to transmit a read enable signal RE to a memory plane 22. Then, old data D0 is latched in a data latch of a data updating circuit 30, and a bit position designating signal S on a system bus 2 is latched in a latch circuit 36. Thereafter, update contents designating data D on the bus 2 is inputted to the circuit 30. Inputted old data D0, signal S, and data D are operated logically by a logic circuit in the updating circuit 30 to attain update data D1. Data D1 is written in a position of the memory plane 22 designated by the signal ADR when the control circuit 21 transmits a write enable signal WE to the memory plane 22. |
