| 摘要 |
PURPOSE:To execute a high-speed parallel-series conversion exceeding an operating speed by a parallel-series converting circuit whose operating speed is low, by distributing and inputting parallel information to plural converting circuits, and selecting and unifying a series information output from each converting circuit. CONSTITUTION:An oscillating clock 14 of an oscillating circuit 1 is frequency- divided 2, applied to a parallel-series converting circuit A3, and also a frequency- divided clock having a different phase is applied to a parallel-series converting circuit B4 through an invertor 7. As a result, a signal 17 and a signal 18 are sent to AND circuits 5, 6, respectively, from a circuit A3 which has converted parallel information A, C to series, and from a circuit B4 which has converted parallel information B, D to series, respectively. OR of its signals 19, 20 is taken by an OR circuit 8, and from the circuit 8, a series signal 21 of the parallel information A, C, B and D is outputted. In this way, by the parallel-series converting circuits 3, 4 whose operating speed is slow, the series information can be brought to a parallel-series conversion at a higher speed than the operating speed of these circuits 3, 4. |
