| 摘要 |
PURPOSE:To access easily a dynamic RAM (DRAM) having no output registers with an optional independent timing clock, by holding and repeating access requests due to the independent clock which does not accord with the clock of the DRAM. CONSTITUTION:When the single clock mode indication due to the independent clock is set from a maintenance control part 6 to a register 8 for the purpose of accessing a DRAM2 from a service processor 5, a clock control part 7 stops clock supply to each control part. The control part 7 supplies the clock to a bus control part 3 at the timing synchronized with a non-control clock for refresh, and set contents of the register 8 are repeated, and a bus use permission signal is supplied from the control part 3 to the processor 5. Consequently, the DRAM having no output registers is accessed easily in accordance with the independent clock due to the service processor or the like without paying attention to the refresh clock or the like. |
