MEMORY ACCESS CONTENTION CIRCUIT

摘要

PURPOSE:To allow even a synchronous type processor to share common memory by sending an access request from the synchronous type processor for the 1st time when a memory access contention circuit confirms that the common memory can be accessed. CONSTITUTION:A memory control circuit MC3 sets a synchronous type processor access state flag SAF which indicates the access start of the synchronous type processor Px to the common memory MEM at a point t5 of time. Then, the synchronous type processor Px sends a read command MR and an address AD to the common memory MEM at a point 6 of time. Consequently, data DT is read out of the common memory MEM and transmitted to the synchronous type processor Px through the memory control circuit MC3 and a bus BUSx. The memory access contention circuit MAC resets the synchronous type processor access state flag SAF at a point t7 of time. Further, various signals are transferred between the synchronous type processor Px and memory control circuit MC3 unconditionally synchronizing with a synchronizing clock CLK.