| 摘要 |
<p>PURPOSE:To detect an error of received data and to write data in memory even after data is ceased by generating a pseudo clock the same as the received data in bit period after the data is ceased. CONSTITUTION:An output Q' of an FF14 goes up to a level H during data reception and a clock synchronizing with a bit period outputted from a one-shot multiplier 12 is generated through an OR gate 133. When the data is ceased, on the other hand, a signal CS' goes up to the level H and a terminal Q of the FF14 is held at the level H. Therefore, the pseudo clock CLK of a clock generating source is generated from a clock selecting circuit 13 through an AND gate 132 and an OR gate 133.</p> |
