| 摘要 |
<p>PURPOSE:To reset normally each CPU by using a counter reset pulse delivered from a working CPU to actuate an autonomous counter corresponding to a CPU which is at pause. CONSTITUTION:A CPU11 which is always working is connected to a CPU12 which works intermittently via a data bus 2 for data transfer. A counter reset pulse 3 is supplied to an autonomous counter circuit 41 from the CPU1. While autonomous reset signals 5 are supplied to both CPU11 and CPU12 from autonomous counter circuits 41 and 42 via a double input OR gate 6 in the form of a CPU reset signal 7. In this case, a switch 8 is provided to supply pulses 3 from both CPU1 and a start signal 9 is supplied to a control terminal from the CPU1. Thus the pulse 3 given from the CPU11 or the pulse 3 from the CPU12 is selected in an inactive mode or active mode of the CPU12 respectively. The selected pulse 3 is delivered to the circuit 42.</p> |
