发明名称 Internal communication arrangement for a multiprocessor system
摘要 A data communication arrangement in which an interface processor effects the transmission of messages between two processors of a multiprocessor system. The interface processor is connected to the communicating processors via direct memory access circuits. A sending processor stores messages in a send buffer in memory of the sending processor and controls a pointer in that memory indicating the loading of message into that buffer. The interface processor reads this pointer and the messages, and writes a pointer and the messages in a receive buffer of a receiving processor. The interface processor limits the loading of new messages into the send buffer by delaying the updating of an unload pointer, creating memory space for new messages, until the receiving processor has processed the transmitted messages. Messages can also be used to initiate the transfer of a block of data from the memory of one processor to that of another. Initialization of the interface processor is a joint effort of the communicating processors.
申请公布号 US4543627(A) 申请公布日期 1985.09.24
申请号 US19810330171 申请日期 1981.12.14
申请人 AT&T BELL LABORATORIES 发明人 SCHWAB, THOMAS F.
分类号 G06F15/16;G06F13/28;G06F15/163;G06F15/167;G06F15/17;H04L13/08;(IPC1-7):G06F15/16 主分类号 G06F15/16
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