| 摘要 |
PURPOSE:To allow a CPU to control a controlled system by providing a means which selects the controlled system on the basis of the 1st address data. CONSTITUTION:The 4-bit control output signal of the CPU1 is supplied to the 1st and the 2nd address data latch circuits 7a and 7b, data input terminals I of data registers 8a-8i, and the data input terminal I of a display control register 9 through a 4-bit bus line 6. The 1st latch circuit 7a latches primary address data on the basis of the output of an AND circuit 3 and the 1st decoder 10a outputs a decoder selection signal to signal lines 11a-11n on the basis of the output of the 1st latch circuit 7a. Further, the output from the Q terminal of the display control register 9 is supplied to a display control circuit 13 and generated by an oscillation circuit 14.
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