发明名称 ENCODING AND DECODING SYSTEM FOR BINARY DATA
摘要 PURPOSE:To perform encoding as specified, to shorten error propagation length, and to reduce a circuit scale when a binary data train is divided into individual bits and the data pattern of every divided bit is converted into a code consisting of two bits. CONSTITUTION:A shift register 4-1 converts original data which is inputted from (a) in a serial state into five-bit parallel data, which is supplied to an encoder 4-2. Then, the encoder 4 converts one-bit data into a two-bit code. Then, an encoder 4 converts one-bit data into a two-bit code. In this case, a code sequence having >=2 and <=7 bits ''0'' between an optional code ''1'' present in the converted code sequence and a code ''1'' appearing next is generated. Thus, the data is encoded to shoten the error propagation length and also reduce the circuit scale.
申请公布号 JPS60186119(A) 申请公布日期 1985.09.21
申请号 JP19840042512 申请日期 1984.03.05
申请人 MITSUBISHI DENKI KK 发明人 IDO KIHEI;FURUKAWA TERUO
分类号 H03M7/14;G11B20/14;H03M5/14;H04L25/49 主分类号 H03M7/14
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