发明名称 ANALOG-DIGITAL CONVERTER
摘要 <p>PURPOSE:To improve the linearity of a remainder class A/D converter (ADC) by leading a pseudo random noise (PRN) to the ADC. CONSTITUTION:An analog signal from an input terminal 10 is stored in a sample-and-hold circuit 11. Since a latch 33 is cleared, only the PRN reaches a D/A converter (DAC)14 through an adder 32 in the 1st path. The PRN is subtracted from an analog input signal at a summing point 15 of the pre-stage of an amplifier 31. Thus, the output of the sample-and-hold circuit 11 reaches the internal ADC12. The 1st path approximation (1st order approximation) output from the ADC12 is inputted to the adder 32 via a latch 33. Then the 1st order approximation is subtracted from the output of the sample-and-hold circuit 11, the result of the subtraction, that is, the remainder is digitized again by the ADC12, the approximation of the 2nd path is added finally to the approximation of the 1st path at an adder 34, and the result is given to an output terminal 40 as the final output of the ADC1 through the latch 35.</p>
申请公布号 JPS60185430(A) 申请公布日期 1985.09.20
申请号 JP19850021580 申请日期 1985.02.05
申请人 YOKOGAWA HIYUURETSUTO PATSUKAADO KK 发明人 DONARUDO AARU HIRAA;CHIYAARUSU KINGUSUFUOODO SUMISU
分类号 H03M1/14;H03M1/00;(IPC1-7):H03M1/14 主分类号 H03M1/14
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