| 摘要 |
PURPOSE:To suppress chip size at its minimum by using buses with time division in a nibble mode circuit processing N-bit information only by one address specification. CONSTITUTION:Two pairs of data buses l5, -l5 and l6, -l6 are precharged by two pairs of precharge circuits provided with TRs Q1, Q2 and Q3, Q4. When the signals phi3, phi4 are turned to the high level, TRs Q5, Q6 and Q7, Q8 are turned on and the information of sense amplifiers A1, A2 corresponding to respective 4-bit information obtained only by one address specification is read out on the buses l5, -l5 and l6, -l6 through the bit lines. Similarly, the information of sense amplifiers A3, A4 is read out through the buses l5, -l5 to be used in common with time division. In information writing in the nibble mode similarly, the processing of 4-bit information or the like based upon one address specification is executed by the two pairs of data buses without using four pairs of data buse, so that the chip size of the nibble mode circuit is suppressed at its minimum.
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