发明名称 SYSTEM TIMING SYNCHRONIZING SYSTEM
摘要 <p>PURPOSE:To suppress the establishment of transition of a master station and also to simplify the transition means by transmitting independently a master packet and a data packet. CONSTITUTION:The master packet A.M transmitted from a station A exists in the 1st block of a frame F(n) and the system timing of each station is synchronized by the packet. Further a data packet B.D of a station B and a data packet C.D of a station C exist in the 2nd block. When the master packet A.M is lost in a frame F(n+1), the station B detects it and transmits a master packet B.M to the 1st block of a frame F(n+2) while it is discriminated that the own station is under the condition to transmit the master packet. Moreover, the timing of the frame F(n) is kept in the frame F(n+1) and reset by the master packet B.M.</p>
申请公布号 JPS60185441(A) 申请公布日期 1985.09.20
申请号 JP19840040664 申请日期 1984.03.03
申请人 FUJI XEROX KK;ANRITSU DENKI KK 发明人 TSUSHIMA HITOSHI;MIYAO FUMIO;MIURA HIDEKI
分类号 H04L7/00;H04L12/00 主分类号 H04L7/00
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