发明名称 |
LARGE CAPACITY MEMORY CIRCUIT |
摘要 |
PURPOSE:To reduce the number of steps of sampling and holding circuits and to reduce circuit size, power consumption and random noise by dividing n small capacity memories into two groups and executing writing and reading alternately. CONSTITUTION:Inputs of holding circuits 1-1-1-n in a serial/parallel conversion part are connected to an analog signal input terminal 3 through sampling circuits 2-1-2-n and the outputs of respective holding circuits 1-1-1-n are inputted to parallel memory circuits 9-1-9-n through switches 6-1-6-n. Respective sampling circuits 2-1-2-n supply an input signal to the holding circuits 1-1-1-n by sampling pulses phi1S-phinS on the basis of sampling signals 5-1-5-n from a control circuit 4. The parallel memory part is divided into two small capacity memory groups 9-1-9-l and 9-(l+1)-9-n and writing and reading in/from these memories are controlled so as not to be superposed each other. |
申请公布号 |
JPS60185285(A) |
申请公布日期 |
1985.09.20 |
申请号 |
JP19840038538 |
申请日期 |
1984.03.02 |
申请人 |
HITACHI SEISAKUSHO KK |
发明人 |
MATSUURA TATSUJI;MATSUI KAZUMASA;FUKAZAWA SHIGERU |
分类号 |
G06F3/05;G01R13/20;G11C7/00;G11C27/00 |
主分类号 |
G06F3/05 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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