| 摘要 |
PURPOSE:To speed up the equivalent converting speed of a sequential comparison A/D converter by operating plural sample-and-hold circuits and plural sequential comparison A/D converters in parallel while making the operating time of them different from each other. CONSTITUTION:The operating timing (n) of the n-th (2<=n<=N) sample-and-hole circuit 1-n is delayed from a timing (b) of a sample-and-hole circuit 1-1 by (n-1)T/N. An operation timing (g) of the n-th sequential comparison A/D converter 2-n is delayed from a timing (f) of the 2-1 by (n-1)T/N. Since the N-set of A/D converter circuits are operated sequentially with a delay of 1/N of the A/D conversion required time T of one A/D conversion circuit in this way, when outputs of the N-set of A/D converting circuits are selected switchingly at each time of T/N after the output of one A/D conversion circuit is extracted by means of a selector 9, the same result as the A/D conversion of the sample hold value at just T/N time is obtained. Then the control of the timing is performed by a controller 8. |
