| 摘要 |
A method of, and a circuit for, estimating true data from distorted digital data signals in which signals, which may have become degraded due to say noise, are clocked into a shift register (12) at a rate higher than the data rate, for example eight times the data rate. The n outputs of the shift register (12) stages are coupled to respective inputs of a majority logic circuit (16) which has (n + 1) inputs. A latching circuit (18) clocked in antiphase to the clocking of the register (12) is coupled to an output of the majority logic circuit (16). The output of the latching circuit (18) is fed back to the (n + 1)th input of the majority logic circuit. …<??>By having a feedback connection a smaller number of samples can be used to reshape a degraded digital data signal than would be the case without feedback. |
