发明名称 CONTROL STORAGE READ SYSTEM
摘要 PURPOSE:To improve the processing efficiency of the system by providing a control storage read circuit activated independently of the circuit being subject to the control storage circuit so as to improve the diagnostic performance of the controller after address information from a CPU is received. CONSTITUTION:A host buffer 210 receives address information from the CPU100, records it and informs it to a control storage read circuit 250 via a lead 211. Then the circuit 250 disconnects a microprocessor 220 governing a control storage device 230 via a lead 251. Then the circuit 250 activates a lead 252, causing the address information stored in the host buffer register 210 to be outputted to a line 213 via a line 212, resulting that the device 230 is subjected to the circuit 250. Then the address information is fed to a register 210 via leads 231, 232, 234 and returned to the CPU100 via a lead 214.
申请公布号 JPS60183655(A) 申请公布日期 1985.09.19
申请号 JP19840040162 申请日期 1984.03.02
申请人 NIPPON DENKI KK 发明人 OOTANI AKIO
分类号 G06F11/22;G06F12/16 主分类号 G06F11/22
代理机构 代理人
主权项
地址