| 摘要 |
PURPOSE:To reset bus occupancy forcibly based on the timing of a timing means and also to relieve the load of a processor if the processor having bus occupancy right is failed by providing a bus supervisory device. CONSTITUTION:When a processor unit acquires the bus occupancy right, the level of a bus state signal 23 is brought into a low state, and the entrace to the operating state is indicated to other processor unit and a bus right control circuit 22. If an error takes place and the unit is brought into the lock state while the low state of the signal 23 is not released, the timing of a timer circuit 212 in a bus supervisory device 21 is advanced and a permission signal 25 is formed after the setting time. A reset circuit 213 receiving it outputs a reset signal 50 being a bus right give-up signal to a bus right request circuit via a system bus so as to give up forcibly the bus occupancy right. Thus, the fault of the unit acquiring the occupancy right is found out easily, the occupancy of bus is abondoned and the load of the CPU is relieved. |
