| 摘要 |
PURPOSE:To obtain a wait generating circuit changed easily by allowing a single wait generating circuit to generate the different number of wait cycles to set them by the software. CONSTITUTION:In accessing an I/O4, a processor 1 writes number of wait cycles from a storage device 3 to a register 10. Then the processor 1 outputs an IOR or an IOW signal to a control bus CB to read or write of a data of an IO device selected by a selection signal CS. A wait generating circuit 11 outputs a read request signal DRQ to a register 10 and also inputs a register data signal RegD and outputs a wait request signal WRQ until the signal RegD is coincident with an incremental counter output signal. The signal WRQ is inputted to the processor 1 and the system is brought into the wait state during the number of wait cycle of required by the I/O4.
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