VARIABLE WORD LENGTH INSTRUCTION PROCESSING SYSTEM

摘要

PURPOSE:To attain multi-direction branches depending on the operand length by reflecting the result of detection of the relation between the operand length or operand data and the operand length and a memory location onto an address control section of a microinstruction. CONSTITUTION:A microinstruction is read from either of a control memory 12 or 13 represented by a control memory address (CSAR)11 and stored in a control memory data register (CSDR)14. The same data is set to a control memory delay data register (CSLDR)9 with a delay. An address of the microinstruction during execution at present. The next branch destination address of the microinstruction is generated by a CSAR generating circuit 10 inputting the content of the CSLDR9, the value of the CSARD8 and the content of a multi-direction branch control register CF7 during the execution of the microinstruction. The result is set to a control memory address CSAR11.