<p>A logic circuit incorporating carry look-ahead in which substantial savings can be achieved as regards the hardware for generating the sum signals and carry signals by a suitable choice of the adder gate, i. e. by utilizing the already present signal ai·bi which is also used for generating the carry look-ahead signal.</p>
申请公布号
EP0155019(A1)
申请公布日期
1985.09.18
申请号
EP19850200134
申请日期
1985.02.07
申请人
N.V. PHILIPS' GLOEILAMPENFABRIEKEN
发明人
VAN MEERBERGEN, JOZEF LOUIS;VEENDRICK, HENDRIKUS JOSEPHIUS M.;WELTEN, FRANCISCUS PETER J. M.;VAN WIJK, FRANCISCUS JOHANNUS A.