| 摘要 |
PURPOSE:To shorten a reading out period of information by extending pulse width of a reset signal to that of time necessary for resetting a bit line potential in a semiconductor memory device where a bit line potential is reset after receiving a chip non-selection signal. CONSTITUTION:When a chip non-selection signal CS' rises, a transistor Q63 is turned on through invertors IV1 and IV2, and a potential at a point (b) falls. An output point (d) of an NOR gate N rises, a transistor Q64 is turned on, and a low level of the output point (b) of an FF3 is latched. Even if the signal CS' falls, a potential at the point (b) is held at a low level. A point (c) becomes a high level through invertors IV4-IV6 after the specific time td expires, the point (d) falls at a low level, the FF3 is reset and the point (b) becomes a high level. After the specific time td expires, the point (c) falls at a low level, and pulse width at the point (c) has more than the specific time td, which is outputted as a bit line reset signal phiR to an output terminal O through invertors IV7 and IV8.
|
