| 摘要 |
PURPOSE:To decrease the number of signal line by storing a parallel data from a CPU and converting a data at each bit of the stored data into a pulse signal of the same period but different in pulse width corresponding to the level to add a signal of a long pulse width to a serial signal. CONSTITUTION:An address bus ADB and a data bus DDB are connected to the CPU1 of an input/output device and a ROM2, ROM3 and an input/output device 100 are connected to the buses ADB and DDB. Input/output circuits 20, 21 are connected to the device 100 via a signal line L1 and electronic components 30, 31 are connected to the circuits 20, 21. The parallel data from the CPU1 is converted into a serial data at the device 100, logical 1 in the address data is assigned to a signal having large pulse width and a logical 0 in the data is assigned to a pulse with a small pulse width so as to form address data A1-A6. Then the data from the bus DDB is outputted sequentially and a start pulse PS longer than the other pulse period is added to the head of a pulse train. Then the number of the signal lines L1 connected to the circuits 20, 21 is decreased. |
