| 摘要 |
PURPOSE:To enhance the use efficiency of a common bus by determining priority levels in the same cycle and transferring data successively in the following data transfer cycles in accordance with priority levels of priority determining signal lines. CONSTITUTION:With respect to a time chart, this system differs from a conventional system in having priority level determining cycles S1 and S2 having the same phase among the priority level determining cycle S1 of priority determination 1 due to a priority level determining signal line 41, the priority level determining cycle S2 of priority determination 2 due to a priority level determining signal line 42, a data transfer cycle TA of a phase A, and a data transfer cycle TB of a phase B. Consequently, even if data transfer requests are generated in both of priority determinations 1 and 2, a higher priority level is given to priority determination 1 to permit the module, whose data transfer is permitted by the priority level determining signal line 41, to transfer data in the phase A. Next, the module whose data transfer is permitted by the priority level determining signal line 42 is permitted to transfer data in the phase B. Thus, the data transfer efficiency is improved in comparison with the conventional system. |
