发明名称 INTER-PROCESSOR CONNECTING SYSTEM
摘要 PURPOSE:To realize a low-cost and efficient multipersonality system by incorporating plural processor units different in characteristic in the system switching and operating them and connecting directly input/output signals of plural processor units to make excess driver/receiver circuits unnecessary. CONSTITUTION:If a processor unit (A) 1 requires mode switching by some cause, contents of a flip-flop 31 are rewritten. That is, data (DAT) for processor switching is given through a CPU bus 4, and a mode A signal and a mode B signal are set to the low level and the high level respectively after a write strobe signal -WRT from a control part 34 comes. Then, the reset terminal of the processor unit B is made active through an NOR gate 33, and a bus control signal is set to the floating state. Reset of a processor unit B is released, and the processor unit B can be operated as a CPU bus mask.
申请公布号 JPS60181865(A) 申请公布日期 1985.09.17
申请号 JP19840037556 申请日期 1984.02.29
申请人 TOSHIBA KK 发明人 MAENO RIYOUZOU
分类号 G06F15/16;G06F9/52;G06F13/362;G06F15/17;G06F15/177 主分类号 G06F15/16
代理机构 代理人
主权项
地址
您可能感兴趣的专利