发明名称 INTERRUPT PROCESSING SYSTEM
摘要 PURPOSE:To execute a series of interrupt processings without setting a central processing unit to the holding state undesiredly, by referring to contents of an input/output system area to enter into execution of interrupt processings and resetting the pending state of interrupt request and input/output interrupt. CONSTITUTION:When receiving an interrupt request signal, a central processing unit 1-0 takes in required information from an input/output system area 6 in accordance with an interrupt unit and performs interrupt processings. If the mode of interrupt in a channel unit is applied, contents of an interrupt pending latch 7 are reset when the central processing unit 1 receives the interrupt request signal from an interrupt request signal transmitting part 15; but if the mode of interrupt in an interrupt level unit is applied, said contents are reset when an interrupt queue is empty. A channel device dequeues interrupts in the interrupt queue in the former mode, and the central processing unit handles unitedly dequeued interrupts in the latter mode. After the latch 7 is reset, an interrupt request indicating latch 16 is reset.
申请公布号 JPS60181860(A) 申请公布日期 1985.09.17
申请号 JP19840037709 申请日期 1984.02.29
申请人 FUJITSU KK 发明人 OINAGA YUUJI;OONISHI KATSUMI;KIKUCHI NOBUYUKI;TATEISHI TERUTAKA
分类号 G06F13/12;G06F13/24 主分类号 G06F13/12
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