| 摘要 |
<p>PROGRAM CODE FETCH ARRANGEMENT The present invention permits any number of pages of data memory to contain program code without the loss of access to the corresponding page of the program code memory. The memory select lead derived from a central processor's control leads is employed by the memory decoding circuitry to distinguish between a program code and a data fetch. This arrangement forces the memory to produce a code fetch from data space of memory, when any one of the pages dedicated to program code is accessed. A fetch control circuit is included between the central processing unit and memory. This fetch circuit obtains program code from the data space in memory when a latch of an input/output port controlled by the central processor unit is set, indicating that a program request is to come from data memory and one of the pages of memory containing program code in the data space is referenced As a result, the memory decoding circuitry detects this request for a fetch as a data fetch, although the processor indicated the fetch as a program code fetch. If the input/output port is not set by the CPU to force a program fetch from data space in memory, program code from the program code memory will be fetched.</p> |
