| 摘要 |
PURPOSE:To perform high-speed transfer by using an FIFO memory at a transfer destination as a buffer RAM and omitting FIFO transfer from the buffer RAM at the transfer destination during data transfer processing between central processors. CONSTITUTION:While a select terminal is held at LOW, the 1st system 1 is allowed to read and write a random access memory 26 as a normal memory, but when the terminal is held at HIGH, the 2nd system 26 uses an I/o port to access the random access 26 apparently on FIFO (first-in first-out) basis. An LOW pulse is applied to a clear terminal 10 to set the address of the random access memory 26 to 0, then an I/O read is made to increase the memory address and read data in, but when I/O writing operation is carried out after the LOW pulse is applied to the clear terminal 10, the memory address is increased every time I/O writing operation is performed, thus writing data. |
