发明名称 |
Process for fabricating pedestal interconnections between conductive layers in an integrated circuit |
摘要 |
A process for fabricating pedestal interconnections between conductive layers in an integrated circuit includes the steps of (a) forming a first conductive layer over a semiconductor substrate; (b) applying a stop etch layer to said first conductive layer, the stop etch layer having a different etch property than the first conductive layer; (c) patterning the first conductive layer and the stop etch layer in an interconnection pattern which includes widened regions wherever a pedestal interconnection is to be formed; (d) selectively etching the stop etch layer until the stop etch layer remains as a stop etch cap only in central sections of the widened regions; and (e) selectively etching the first conductive layer to a selected depth whereby a pedestal is formed underneath the stop etch caps. The following optional steps may be added: (f) applying a layer of an insulating material over the first conductive layer; and (g) planarizing the insulating layer to expose the tips of the pedestals.
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申请公布号 |
US4541893(A) |
申请公布日期 |
1985.09.17 |
申请号 |
US19840610450 |
申请日期 |
1984.05.15 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
KNIGHT, COLIN W. T. |
分类号 |
H01L21/768;(IPC1-7):C23F1/02;B44C1/22;C03C15/00;C03C25/06 |
主分类号 |
H01L21/768 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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