| 摘要 |
PURPOSE:To attain surely matching in phase of each data signal by using a reference clock to detect a phase difference between a confirming synchronizing signal inserted in an input data and a reference synchronizing signal thereby controlling the delay amount of the input data. CONSTITUTION:A data part DATA inputted to a phase correction circuit DPC is inputted to a buffer memory circuit 32 via a variable delay circuit 31. A data clock DCL inputted synchronizingly with the DATA is inputted to a latch signal forming circuit 36 having a click phase detecting circuit 35. A system clock SCL being a reference is inputted to the circuit 36, the DCL and the SCL are compared, either the SCL or the -SCL is selected from the result of comparison to outputs latch signals CK1, CK2 of the circuit 32, and after the output of the circuit 31 is fetched to the circuit 32, a signal DO is outputted. The phase difference between the confirming synchronizing signal ISYNC inserted to the DATA and the reference synchronizing signal RSYNC is detected at a phase difference detecting circuit 40 by using the DO, a phase difference signal DEF controls the circuit 31 to make the phase of the ISYNC and the RSYNC match. |
