发明名称 DELAY CIRCUIT
摘要 <p>PURPOSE:To miniaturize the circuit and to set easily the delay time by providing a full band transmission filter comprising inductances connected in series and a capacitor connected in parallel with the midpoint of the inductances between stages of inverting gates consisting of an emitter coupling logical circuit giving a prescribed time of delay to a signal string between the inverting gate stages. CONSTITUTION:The full band transmission filter 11 is provided in place of a coaxial cable and sets an optional delay time of nearly ns (nano sec) to high- speed data inverted by the emitter coupling logical (EOL) circuit. The capacitor 22 is connected in parallel with the midpoint of the inductances L211, L212 connected in series and grounded in the full band transmission filter 11. The filter 11 is characterized in that the amplitude is transmitted as it is over the entire frequency range and only the phase is shifted, allowing to set a prescribed delay time. A desired delay time is obtained by providing the full band transmission filter to the inter-stage of the ECL circuit and setting optionally the constant and it is easy to change the delay time. Since the filter is formed by combining high frequency LC, the circuit is miniaturized.</p>
申请公布号 JPS60180314(A) 申请公布日期 1985.09.14
申请号 JP19840036797 申请日期 1984.02.28
申请人 FUJITSU KK 发明人 SUZUKI TERUHIKO;ARAI MASANORI;OKADA KIMIYOSHI;TSUDA TAKASHI
分类号 H03H11/26;H03H7/09;H03H7/32;H03K5/13 主分类号 H03H11/26
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