| 摘要 |
<p>PURPOSE:To attain data communication with an asynchronous transmitter by receiving a start pulse and a data block, generating a pulse corresponding to the data block and generating a clock having a phase difference corresponding to each bit of the reception data and a period to convert the reception data in parallel. CONSTITUTION:Serial data are converted in parallel and the result is fed to a register 3, and an N-bit parallel data 4 is formed until the next data comes. Moreover, the wave head of the data 1 is differentiated at a differentiating circuit 6 by using a basic clock 5 of a receiver and an FF7 is set. A gate 8 passes only the first one pulse in a differentiating circuit by using an output of an FF8. A counter 9a is counted only with the set state of the FF7, the phase T3 is decided in response to a value of a preset data D1 and the clock of a period T2 is fed to an S/P converter 2. A counter 9b receives a carry signal of the counter 9a and resets the FF7 by using a pulse passing through a time corresponding to the bit number N depending on the preset data D2 and the latch timing of the register 3 is obtained. A clock 5 is applied in this case.</p> |
