| 摘要 |
PURPOSE:To attain a circuit with less number of connecting wires and power consumption and low voltage and high speed operation by providing a logical circuit whose terminal is connected to a load MOS transistor (TR) and consisting of the one conduction channel load MOS TR and an MOS TR of the opposite conduction channel and an inverter circuit. CONSTITUTION:Suppose that a control signal phi is an active high level and input signals IN1, IN2 are at a low level at first, a PMOS TRQp2 is turned on, and NMOS TRs Qn3, Qn4 are turned off, then an output signal OUT1 is at a high level and an output signal OUT2 is at a low level. When the control signal is at an inactive low level, the NMOS TRQn1 is turned off next. When the input signal IN2 reaches a high level, the NMOS TRQn4 is turned off. Since the NMOS TRQn3 is turned off, the level of the output signal OUT1 is unchanged. When the input signal IN1 reaches a high level and the NMOS TRQn3 is turned on, the level of the output signal OUT1 is lowered, the level of the output signal OUT2 is increased, the PMOS TRQp2 is turned off and the power consumption is nearly zero. |
