发明名称 |
MEMORY CIRCUIT |
摘要 |
PURPOSE:To accelerate both the reading speed and precharging speed by setting the precharging potential of a bit line at a high sensitivity area of a sense amplifier in case the simultaneous reading of two ports is designated to the same memory cell of a two-port RAM. CONSTITUTION:Bit lines 5 and 5' are set at the power supply voltage; while bit lines 6 and 6' are set at the ground potential respectively. Then a charge redistribution is produced between lines 5 and 6 as well as 5' and 6' when FET25-28 are turned on. In this case, the potentials of lines 5 and 6 set after the redistribution are equal to the mean value of the value at which both terminals are previously precharged and set at levels where the sensitivity of a sense amplifier is highest. The same value of potential is also obtained between lines 5' and 6'. Then the lines 5 and 6 are charged at the potential of a point (a); while lines 5' and 6' are charged at the potential of a point (b) respectively. Thus the sense amplifier can decide correctly ''1'' and ''0''. |
申请公布号 |
JPS60179992(A) |
申请公布日期 |
1985.09.13 |
申请号 |
JP19840034464 |
申请日期 |
1984.02.27 |
申请人 |
NIPPON DENSHIN DENWA KOSHA |
发明人 |
MATSUTANI YASUYUKI;YAMAUCHI HIROKI |
分类号 |
G11C11/41;G11C11/34;(IPC1-7):G11C11/34 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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