| 摘要 |
PURPOSE:To access a common memory without holding a CPU and to improve the data transfer speed of an one-way memory by connecting said memory between a main CPU and a sub-CPU. CONSTITUTION:The one-way memory 3 is formed between the main CPU1 and the sub-CPU2. When a CPU1 is to write data in the memory 3, the CPU1 checks whether an acknowledge flag ACKF is set up in a control logical circuit 8, and when the flag ACKF is set up, sends write data to a data bus DB1. Consequently, an address signal is supplied to the memory 3 and a write enable signal is supplied to a terminal WE to execute writing. At the time of reading by a CPU2, the CPU2 checks whether an interruption flag IRQF is set up in a control logical circuit 9 or not, and when no flag is set up, sends the address to AB2 to read out data from the memory 3. |
