| 摘要 |
<p>PURPOSE:To facilitate easy production and change of a desired sequence control signal by performing the arithmetic processing according to the output given from an optional stage of a ring counter and producing a desired timing signal according to the signal produced from said arithmetic processing. CONSTITUTION:A ring counter is provided with a flip-flop 20 and a shift register 21, and the only logic ''1'' is circulating with a shift and synchronously with CLOCK as shown between As through Is. A signal SELECT selects Js and Ms with logic ''0'' and Ks and Ns with logic ''1'' respectively and delivers them through a selection signal 22. Under such conditions, a signal Js is first selected since the SELECT is set at ''0'' and an output signal Ls of a register 29 is inverted to logic ''1'' from logic ''0'' by the rise of the signal CLOCK. Then the second pulse of the Js is produced. In the same way, the Ls is inverted to logic ''0'' from logic ''1'' by the rise of the next CLOCK signal. Then a signal Os is also obtained by a signal Ms.</p> |
