发明名称 Circuit arrangement for monitoring a rectangular clock signal
摘要 The arrangement described for monitoring a rectangular clock signal contains a low-pass filter with a low cut-off frequency by means of which the average of the clock signal to be monitored is obtained. A window comparator following the low-pass filter outputs a binary one at its output when the average of the clock signal is not within predeterminable tolerance limits. This indicates not only the failure of the clock signal but also, for example, the degeneration of the clock pulses to needle pulses.
申请公布号 DE3408588(A1) 申请公布日期 1985.09.12
申请号 DE19843408588 申请日期 1984.03.09
申请人 PHILIPS PATENTVERWALTUNG GMBH 发明人 SCHMIDT,LUITFRIED,DIPL.-ING.
分类号 H03K5/19;(IPC1-7):H03K5/19 主分类号 H03K5/19
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