发明名称 ELECTRONIC APPLIANCE
摘要 PURPOSE:To enable a higher data processing speed in a printer or the like by allowing the second processing means to perform a specified processing with a CPU in an interval of the processing operation with the first process means. CONSTITUTION:In the subsequent writing cycle, information 121 from a RAM106 is OR-processed with an OR108 by a pulse 122 via a register 107 and is written into the RAM106 by a pulse 124 as in the preceding cycle. Meanwhile, a CPU prepares the subsequent data 101 and address information 109 and gets on standby state based on a signal 125. Upon the end of the writing, a main controller 112 clears a register 113 by a pulse 126 and releases the CPU from the standby state turning the signal 125 to L. New address information 109 and data 101 are latched into registers 110 and 102 and the main controller 112 enters the writing cycle of the subsequent RAM. This reduces the load of the CPU to improve the data processing speed.
申请公布号 JPS60178072(A) 申请公布日期 1985.09.12
申请号 JP19840033613 申请日期 1984.02.24
申请人 CANON KK 发明人 UEDA SHIGERU
分类号 G06F3/12;B41J5/30;G06F15/16;G06K15/12;G09G1/00;G09G5/00 主分类号 G06F3/12
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