| 摘要 |
PURPOSE: To enhance the accuracy of time analysis and the upper limit of a counting rate, by inputting an objective signal to front edge, rear edge and reference comparators from a delay circuit through a specific voltage dividing circuit and taking the AND condition of the outputs of the front edge, rear edge and reference comparators. CONSTITUTION:A delay circuit for inputting a pulse like analogue signal A is constituted of delay elements 11, 12 and resistors 13, 14 while a voltage dividing circuit is constituted of a voltage divider consisting of resistors 21, 22 connected in series and a voltage divider consisting of resistors 23, 24 and the connection point K of the elements 11, 12 is connected to the connection point L of both voltage dividers. In addition, a comparator circuit is constituted of front edge, rear edge and reference comparators 31, 33, 32 while the voltage at the point K and reference voltage VD are inputted to the comparator 32, the voltages at the connection point M and at the connection point of the resistors 21, 22 to the comparator 33 and the voltages at the connection point N and the connection point of the resistors 23, 24 to the comparator 31. The outputs of said comparators 31, 32, 33 are inputted to AND circuits 41, 42 of a judge circuit 40 and the wave form of the signal A is discriminated on the basis of double condition judge signals thereof.
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