发明名称 BIT SYNCHRONIZATION CONTROLLING SYSTEM
摘要 PURPOSE:To execute automatically a bit synchronization between a reference data and a data to be synchronized, by counting the number of errors being a dissidence output in a bit comparing circuit, at every prescribed section, and controlling a data shifting means so that a counting value to an error counting circuit attains the minimum. CONSTITUTION:At the time of an operation for acquisition of synchronism, in case an error counting value is smaller than the minimum storage value, the contents of the minimum storing circuit 19 are updated so that its error counting value attains the next minimum storage value. Also, in case when the counting value is larger than the minimum storage value, a synchronization protecting circuit 20 controls a shift register 13 by a comparison output from the minimum comparing circuit 18, and a data to be synchronized is shifted successively, for instance, by 1 bit each to a reference data. Also, the updated minimum storage value of the minimum storing circuit 19 goes to small in a synchronizing state, therefore, when a storage value of the minimum storing circuit 19 goes to below a prescribed value, the synchronization protecting circuit 20 regards it as an acquisition of synchronism. As a result, updating of the storage value of the minimum storing circuit 19 is stopped, and also the control of the shift register 13 is stopped.
申请公布号 JPS60177746(A) 申请公布日期 1985.09.11
申请号 JP19840032466 申请日期 1984.02.24
申请人 FUJITSU KK 发明人 INANO SATOSHI
分类号 H04L1/00;H04L7/00 主分类号 H04L1/00
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