| 摘要 |
PURPOSE:To obtain a level compensating function of an output signal for a level limiter circuit by providing a CMOS inverter circuit which works on the level limiter voltage after receiving the inverse signal of an input signal with the output point of said inverse signal connected to an output terminal to the level limiter circuit. CONSTITUTION:A CMOS inverter circuit is provided to prevent the level reduction of an output signal phi' due to a leakage current. This inverter circuit contains a p channel MOSFETQ6 and an n channel MOSFETQ7 which are actuated by the level limiter voltage VcL together with an output terminal connected to an output terminal OUT. While an input terminal of the inverter circuit is connected in common to an input terminal of another CMOS inverter circuit which produces an input signal phi and receives supply of an inverse signal phi''. The FETQ6 is provided with the conductance characteristics of such a small degree that compensates the level reduction due to the leakage current. |
