| 摘要 |
PURPOSE:To flatten the surfacen of a device while improving the workability by means of reducing the diffusion process. CONSTITUTION:A P<+> layer 16 and an N<+> layer 18 are selectively coated coated by means of spin coating process and then these two layers 16, 18 are thermal- diffused at high temperature for a long time until they reach specific depth. At this time, the P<+> layer 16 and the N<+> layer 18 form respective diffusion regions in an N type layer 12 since any part other than patterning is blocked by an oxide film 17. Next an oxide film 19 made of SiO2 is grown on overall surface of a wafer and then the oxide film 19 directly above the P<+> layer 16 is patterned to expose the P<+> layer 16 forming an N<+> layer 20 in said layer 16. Through these procedures, the N<+> layer 18 diffused in the N-layer 12, the P<+> layer 16 and the N<+> layer 20 diffused in the P<+> layer 16 may respectively fill the roles of a collector region, a base region and an emitter region of a transistor. |
