| 摘要 |
PURPOSE:To attain high speed accessing by quickening the detection timing of a line cross and conducting it together with the address calculation to minimize the length of waiting caused by the line cross. CONSTITUTION:An effective address generator EAG4 calculates the address according to the content of a base register BR1, an index register XR2 and a displacement register DR3 and generates an effective address. This address is stored in the 1st and 2nd effective address registers EAR I , EARII, a line cross detecting circuit 6 quickens the detecting timing of the line cross and detects it in parallel with the address calculation. When the line cross is detected next, after the first line data is read, the buffer access is executed again at the succeeding cycle. Thus, the address of the next line stored in the EAR I is fed to the memory BS so as to quicken the access. |
