| 摘要 |
<p>PURPOSE:To omit an FIFO register, to make a device profitable in an econonical view point and to improve processing efficiency by controlling the execution time of a read/write instruction to a peripheral circuit for an one-chip CPU on the basis of an external signal. CONSTITUTION:When a wait signal WS is generated from an FF circuit 201a, an FF circuit 11f-1 in an executionn time control circuit 11f for the one-chip CPU11 is set up by a clock pulse CLP and the wait signal WS is generated synchronously with the clock pulse. At the generation of the wait signal WS, i.e. at the time of access from a main processor 101a to a RAM101c, the start of the execution cycle of the read/write instruction from the one-chip CPU is inhibited. At the end of the access, an address signal outputted from the RAM101c to an address bus 301b is erased and the FF circuit 201a is reset.</p> |
