发明名称 INSTRUCTION SIGNAL TRAIN PROCESSING CIRCUIT
摘要 PURPOSE:To decrease the congestion probability of a buffer circuit by scanning a first-out buffer possible for storing plural instruction signals, linking it to an execution processing section and setting a flag whether the processing is in operation or finished to squeeze the location of idle instruction after the end of execution. CONSTITUTION:Four instruction signals C0-C3 are stored in a buffer memory BM in the order of arrival. The instruction signals C0-C3 have information at which execution processing section is to be executed, and a scanning circuit EXP scans it and links the execution processing sections as C0 E I ,...,C3 EIV. Idle instruction is confirmed by an end flag provided to the execution processing section is confirmed in this case and an establishing flag is set. This flag is utilized to discriminate whether the instruction signal at scanning is before or after linking, the instruction signal when the end flag is set is excluded by a shift circuit SHC with the changeover of a selector SEL and the buffer memory conducts shift operation.
申请公布号 JPS60173634(A) 申请公布日期 1985.09.07
申请号 JP19840024132 申请日期 1984.02.10
申请人 FUJITSU KK 发明人 AKAO TAKASHI
分类号 G06F15/16;G06F9/38;G06F15/167;H04Q3/545 主分类号 G06F15/16
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