| 摘要 |
PURPOSE:To verify the logical simulation of a digital logical circuit at a high speed by performing every macro logic unit. CONSTITUTION:A pointer 51 which indicates the current clock phase of simulation specifies entries of, for example, two kinds of two-phase clocks which differ in phase in a corresponding time ring 52, and a macro calculation unit table 54 is looked up. An output value 531 of every macro calculation unit forming an event of a combinational circuit surrounded with flip-flops made in macro structure as a pool type by combining gates, a table address 532 of every macro calculation unit, a queue pointer 533 between events, etc., are outputted to obtain an event 53, so that simulation is performed by processing based upon macro logical units. Therefore, an event of every gate unit need not be generated and the logical simulation of the digital logical circuit having many gates is verified at a high speed. |
